(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device having a tapered-mesa side-wall film, and more particularly, to an improvement of the structure of an interlayer dielectric film embedding therein an interconnection layer.
(b) Description of the Related Art
A multi-layer interconnection structure is generally employed in conventional semiconductor devices, such as a DRAM, for reducing the occupied area of the semiconductor devices. The multi-layer interconnection structure increases the integration density of the semiconductor device in association with the fine fabrication processes. The resultant semiconductor devices having a higher integration density generally have a higher aspect ratio and a smaller distance between each adjacent two of the interconnects due to the smaller dimensions of the devices in the horizontal directions.
FIGS. 3A to 3E show consecutive fabrication steps of a process for fabricating a conventional multi-layer interconnection structure by using a two-layer hard mask. A metallic conductive layer 11a is first deposited on an underlying silicon oxide film 10, followed by deposition of the two-layer hard mask including an insulator film 12 and a silicon oxide film (oxide film) 13 consecutively as viewed from the bottom. The insulator film 12 may be a silicon nitride film (nitride film) having a sufficient etch selectivity relative to the oxide film 13. A photoresist film is then formed on the oxide film 13 by coating, followed by patterning thereof to obtain a photoresist pattern 14. The insulator film 12 and oxide film 13 are then etched by using the photoresist pattern 14 as a mask, to obtain the structure of FIG. 3A.
Subsequently, the photoresist pattern 14 is removed, followed by etching the metallic conductive film 11a to configure bit lines 11 having a specified width by using the insulator film 12 and oxide film 13 as a mask, as shown in FIG. 3B. Thereafter, as shown in FIG. 3C, another insulator film 15 is deposited on the entire surface, followed by etch-back thereof to configure side-wall films 16 on the bit lines 11a and corresponding insulator films 12, as shown in FIG. 3D. After this etching step, a portion of the oxide film 13 may be left on the insulator film 12, as illustrated by the dotted line in FIG. 3D.
After forming the side-wall film 16, an interlayer dielectric film 17 is deposited to entirely embed therein the bit lines 11, insulator films 12 and side-wall films 16, as shown in FIG. 3E. It is to be noted that a defect, or void, is formed in the interlayer dielectric film 17 between side-wall films 16 (or bit lines 11). The void is likely to occur in the case of a smaller distance between the bit lines 11 and the case of a higher aspect ratio of the insulator films 12 and side-wall films 16. In other words, a defective embedding structure of the interlayer dielectric film 17 may occur in the case of a smaller distance between the adjacent side-wall films 16 and a larger depth of the side-wall films 16.
The two-layer hard mask may be replaced by a single-layer hard mask for patterning the bit lines 11. FIGS. 4A to 4F show consecutive fabrication steps of another process using the single-layer hard mask in another conventional technique.
A metallic conductive film 11a and an insulator film 12 are consecutively formed on an underlying oxide film 10. Thereafter, a photoresist film is formed on the insulator film 12 by coating, followed by patterning thereof to form a photoresist pattern 14. By using the photoresist pattern as an etching mask, the insulator film 12 is etched, as shown in FIG. 4A. After removing the photoresist pattern 14, the metallic conductive film 11a is then patterned using the insulator film 12 as a mask to configure bit lines 11 having a specified width just under the insulator film 12, as shown in FIG. 4B. An insulator film 15 is then deposited on the entire surface, as shown in FIG. 4C, followed by etch-back thereof to configure side-wall films 16 on both sides of the bit line 11 and the insulator film 12, as shown in FIG. 4D.
After the etch-back step, the insulator film 12 on the bit line 11 has a reduced thickness compared to the case using the two-layer hard mask, as illustrated by the dotted line in FIG. 4D. Subsequently, an interlayer dielectric film 17 is deposited to embed therein the insulator films 12 and the side-wall films 16, as shown in FIG. 4E. In this case using the single-layer hard mask, since the space between adjacent side-wall films 16 has a smaller depth, the defective embedding structure of the interlayer dielectric film such as encountered in the case of the two-layer hard mask is less involved in this case.
After forming the interlayer dielectric film 17, the interlayer dielectric film 17 is etched while using the insulator film 12 and the side-wall films 16 as an etch stopper in an self-alignment etching technique in order to form a contact hole for receiving therein a contact, i.e., self-aligned contact, for a capacitor between the bit lines 11. In this case of the single-layer hard mask, there may arise a problem that a short-circuit failure occurs between the self-aligned contact and one of the bit lines 11, as illustrated in FIG. 4F, due to the insufficient thickness of the insulator film 12 which may cause an exposed surface of the bit lines 11 during after self-alignment etching.
It is to be noted that a defective embedding structure of the interlayer dielectric film is more likely to occur along with the development of the finer patterning process to reduce the space between adjacent interconnect lines. As described above, the two-layer hard mask causes the defective embedding structure due to the increased aspect ratio, wherein the space between the adjacent side-wall films has a larger depth. On the other hand, the single-layer hard mask may cause a short-circuit failure due to reduction of the thickness of the insulator film and thus reduction of the etching margin during etching for the contact hole receiving therein the self-aligned contact, although there is some improvement in the embedding structure itself.
Patent Publication JP-A-2000-31277 describes an improvement in the embedding structure formed by using the single-layer hard mask, wherein the embedding interlayer dielectric film is formed after removing the top corners of the insulator film on an aluminum interconnect line. The described technique can reduce the effective aspect ratio by increasing the space between the adjacent insulator films in the vicinity of the top thereof due to the removal of the top corners of the dielectric film. However, this technique does not solve the above problem of the short-circuit failure because the reduced thickness of the insulator film reduces the etch margin during etching for the self-aligned contact hole.